parameter ROM_WIDTH = <ram_width>;
   parameter ROM_ADDR_BITS = <ram_addr_bits>;

   reg [ROM_WIDTH-1:0] <rom_name> [(2**ROM_ADDR_BITS)-1:0];
   reg [ROM_WIDTH-1:0] <output_data>;

   <reg_or_wire> [ROM_ADDR_BITS-1:0] <address>;
   
   initial
      $readmemh("<data_file_name>", <rom_name>, <begin_address>, <end_address>);

   always @(posedge <clock>)
      if (<enable>)
         <output_data> <= <rom_name>[<address>];