327"ns" - address 2018h latched by the falling edge of ALE
332"ns" - code E4h fetched at the rising edge of /PSEN
          - quick look into table - E4=CLR A
333"ns" - address 2019h latched 
338"ns" - code from this address fetched 
          - this is a dummy read, as CLR A
          is a 1-byte instruction taking 1 instruction cycles,
          and there are 2 code fetches in each instruction cycle
339"ns" - address 2019h latched
344"ns" - code 93h fetched (this time it is going to be executed)
          - 93=MOVC A,@A+DPTR (DPTR was previously set to 0)
345"ns" - address 201Ah latched
350"ns" - another dummy read, this time the MOVC is a 1-byte, but
          2 cycle instruction, so there are 4 fetches altogether;
          1 fetches the real opcode, 1 (the last) performs the
          MOVC read itself, so there are 2 dummy reads in between
351"ns" - address 201Ah latched again
356"ns" - the 2nd dummy read
357"ns" - read from internal code starts. Although ALE cycled, as
          there is a no real external bus cycle, P2 is restored
          to the state latched into the P2 SFR, which is FFh from
          the reset (there was no code executed which would write     
          explicitly into P2). P0 is floated, but it is not seen
          as it does not have pullups, so the previous state is
          retained on the parasitic capacitance of the pins/bus.
358"ns" - /PSEN was NOT asserted, indicating internal code memory
          read. Unfortunately, the value at internal code memory 
          address 0000h (which is where A+DPTR points) is 02h,
          the same value as the "floating" value of P0,
          (both being the first byte of LJMP), so we don't know
          whether this value is output onto the external bus (P0)
          or not (but I guess not).
362"ns" - the "internal /PSEN" ends, the next address is output 
          onto P0 and P2
363"ns" - address 201Ah latched
368"ns" - the "real" opcode 02h is fetched
  etc.