library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_arith.all ; use ieee.std_logic_unsigned.all; entity rx is port(mr :in std_logic; clk_8 :in std_logic; --8 x oversample clock man_in :in std_logic; cd :out std_logic; data_clk :out std_logic; data_out :out std_logic); end rx; architecture rtl of rx is signal clk_1 :std_logic; signal net_in_hi2lo_shift :std_logic_vector(1 downto 0); signal in_trans :std_logic; signal net_in_hi2lo :std_logic; signal net_in_lo2hi :std_logic; signal filter :std_logic; signal filter_lo2hi :std_logic; signal filter_hi2lo :std_logic; signal filter_hi2lo_shift :std_logic_vector(1 downto 0):="00"; signal mr_and_filter_hi2lo :std_logic; signal mr_and_filter :std_logic; signal cd_sys :std_logic; signal data_clk_out :std_logic; signal cd_shift :std_logic_vector(5 downto 0):="000000"; signal mux_sel_ck :std_logic; signal count_8 :std_logic_vector(2 downto 0):="000"; signal count_6 :std_logic_vector(2 downto 0):="000"; signal count_5 :std_logic_vector(2 downto 0):="000"; signal count_4 :std_logic_vector(1 downto 0):="00"; begin --generate main clock from oversample clk clk_8_divider : process (mr,clk_8) begin if mr='0' then count_8<="000"; elsif rising_edge(clk_8) then count_8 <= count_8 + "001" ; clk_1 <= not (count_8(2)) ; end if ; end process clk_8_divider; -- shift register shift_reg : process (mr,clk_8) begin if mr = '0' then net_in_hi2lo_shift <= "00"; elsif rising_edge(clk_8) then net_in_hi2lo_shift <= net_in_hi2lo_shift(0) & man_in; end if; end process shift_reg; -- transition detector -- detects change in input state net_in_hi2lo <= (not net_in_hi2lo_shift(0)) and net_in_hi2lo_shift(1); net_in_lo2hi <= net_in_hi2lo_shift(0) and (not net_in_hi2lo_shift(1)); in_trans <= net_in_hi2lo or net_in_lo2hi ; ---syncronise samples to middle of main clock sample_filter: process (mr,clk_8) begin if mr = '0' then count_6 <= "000"; filter <= '0'; elsif rising_edge(clk_8) then if (filter = '1') then if count_6 = "101" then count_6 <= "000"; filter <= '0'; else count_6 <= count_6 + "001"; filter <= '1'; end if; else if (in_trans = '1') then filter <= '1'; count_6 <= count_6 + "001"; else filter <= '0'; count_6 <= "000"; end if; end if; end if; end process sample_filter; transition_filter : process (mr,clk_8) begin if mr = '0' then filter_hi2lo_shift <= "00"; elsif mr='1' and rising_edge(clk_8) then filter_hi2lo_shift <= filter_hi2lo_shift(0) & filter; end if; end process transition_filter; filter_lo2hi <= filter_hi2lo_shift(0) and (not filter_hi2lo_shift(1)); data_out_gen: process (mr,clk_8) begin if mr = '0' then data_out <= '1'; elsif rising_edge(clk_8) then if (filter_lo2hi = '1') then data_out <= man_in; end if; end if; end process data_out_gen; filter_hi2lo <= (not filter_hi2lo_shift(0)) and filter_hi2lo_shift(1); mr_and_filter_hi2lo <= mr and (not filter_hi2lo); --extract data clock data_clock: process (mr_and_filter_hi2lo,clk_8)begin if (mr_and_filter_hi2lo = '0') then data_clk_out <= '1'; count_4 <= "00"; elsif rising_edge(clk_8) then if (count_4 = "10") then data_clk_out <= '0'; else count_4 <= count_4 + "01"; data_clk_out <= '1'; end if; end if; end process data_clock; mr_and_filter <= mr and not (filter); carrier_detect: process (mr_and_filter,clk_8) begin if (mr_and_filter = '0') then count_5 <= "000"; cd_sys <= '1'; elsif rising_edge(clk_8) then if (count_5 = "110") then cd_sys <= '0'; else count_5 <= count_5 + "001"; cd_sys <= '1'; end if; end if; end process carrier_detect; cd <= cd_sys; carrier_detect_shift : process (mr,clk_1) begin if mr = '0' then cd_shift <= "000000"; elsif mr='1' and rising_edge(clk_1) then cd_shift <= cd_shift(4 downto 0) & cd_sys; end if; end process carrier_detect_shift; mux_sel_ck <= cd_shift(5) and (not cd_sys); data_clk <= clk_1 when mux_sel_ck = '1' else data_clk_out; end rtl;