With <u>EXTRAM=0</u> ... [skiped] ...
An access to external data memory locations highter
than the accessable size of the XRAM will be performed with
the MOVX DPTR instructions in the same way as in the standard
80C51 with P0 and P2 as data/address busses, and P3.6 and P3.7
as write and read timings signals.