
pc_clk                    equ INT0
pc_data                   equ T0
kbd_clk                   equ INT1
kbd_data                  equ RD
interrupt_on_pc_clk       equ EX0
interrupt_on_kbd_clk      equ EX1

kbd_work_byte             equ 8
kbd_num_bits              equ 9
pc_work_byte              equ 0xa
pc_num_bits               equ 0xb
kbd_buf_read_index        equ 0xc
kbd_buf_write_index       equ 0xd
pc_buf_read_index         equ 0xe
pc_buf_write_index        equ 0xf

kbd_buf                   equ 0x10
pc_buf                    equ 0x18

previous_was_left_shift   equ 0
previous_was_right_shift  equ 1
previous_was_0xf0         equ 2
previous_was_0xed         equ 3
translate                 equ 4
kbd_buf_is_empty          equ 5
pc_buf_is_empty           equ 6
receiving_from_kbd        equ 7
receiving_from_pc         equ 8

; - - - - - - - -

org 0
    sjmp  start
org 3
    ljmp  pc_clk_isr
org 0xb
    ljmp  t0_isr
org 0x13
    ljmp  kbd_clk_isr

; - - - - - - - -

start:
    mov   kbd_work_byte, #0
    mov   kbd_num_bits, #0
    mov   pc_work_byte, #0
    mov   pc_num_bits, #0
    mov   kbd_buf_read_index, #0
    mov   kbd_buf_write_index, #0
    mov   pc_buf_read_index, #0
    mov   pc_buf_write_index, #0
    mov   0x20, #0
    mov   0x21, #0
    mov   SP, #0x21
    mov   DPTR, #table
    mov   TMOD, 00000010b
    mov   TH0, #-30

    setb  kbd_buf_is_empty
    setb  pc_buf_is_empty

    setb  interrupt_on_pc_clk
    setb  IT0
    setb  interrupt_on_kbd_clk
    setb  IT1
    setb  ET0
    setb  EA

    clr   P3.5  ; power up the keyboard

...

; - - - - - - - -

pc_clk_isr:
    push  PSW
    push  0
...
    setb  TR0
    setb  receiving_from_pc
    mov   pc_num_bits, #0

pci_exit:
    pop   0
    pop   PSW

    reti

; - - - - - - - -

t0_isr:
    clr   TR0
    clr   interrupt_on_pc_clk
    push  PSW
    push  ACC
    push  0
...
    ; at this point the byte received is in pc_work_byte
    clr   TR0
    mov   pc_num_bits, #0
    clr   receiving_from_pc
...
t0i_exit:
    pop   0
    pop   ACC
    pop   PSW
    setb  interrupt_on_pc_clk

    setb  TR0

    reti

; - - - - - - - -

end
