;|******** AT89C51RD2 XRAM CODE ******|
;| 
;|
:|*************************************

mov A,#83h ;load register and set AUXR reg. (83h) to enable XRAM
mov R0,A   ;size of 1792 bytes (max), XRAM is indirect
mov @R0,#10h ;AUXR = XRAM enabled, max size

mov A,#10h  ;Load DPTR with address for reading data table
mov DPL,A
mov A,#06h  ;DPTR = 0610h
mov DPH,A
;note data table starts at 0610h in ROM

READ_TABLE:
  clr A
  movc A,@A+DPTR ;Get byte from data table in ROM
  movx @DPTR,A   ;and store in XRAM, same address for convenience
  
  inc DPTR  ;increment DPTR to prepare for next add./iteration
  
  clr TI
  mov SBUF,A ;send out byte value for verification (serial)

wait_serial1: 
   jnb TI, wait_serial1 ;Wait for transmission

   mov A,DPL
   cjne A,#69h, READ_TABLE ;Loop until last byte was read

XRAM_TEST_READ:
   mov A,#10h
   mov DPL,A
   mov A,#06h  ;DPTR will = 0610h
   mov DPH,A  ;Place address of byte data test in DPTR
              ;(indirect addressing required for XRAM)
XRAM_READ_LOOP:
   movx A,@DPTR ;get byte from XRAM and loop until all read

   clr TI
   mov SBUF,A
wait_serial2:
   jnb TI,wait_serial2

   inc DPTR
   mov A,DPL
   cjne A,#69h,XRAM_READ_LOOP ;loop until last byte read

;*** END ***