;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

	SP		equ	81h			;stack pointer
	DPL		equ	82h			;low byte of data pointer
	DPH		equ	83h			;high byte of data pointer
	DPS		equ	86h			;data pointer select sfr
	PMR		equ	0C4h			;power management sfr

	SUCCESS		equ	90h			;P1.0
	FAIL		equ	91h			;P1.1

	TESTER		equ	30h
	TEST_COUNT	equ	31h
	
;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

			org	0000h

			ajmp	START
							
			org	0080h

;---------------------------------------------------------------
START:

			mov	SP,#7Fh
			orl	DPS,#00010000b		;auto-increment DPTR
			orl	PMR,#00000001b	        ;internal 1kB sram enabled

			setb	SUCCESS			;LEDs off
			setb	FAIL

			clr	A
			mov	DPTR,#0000h

WRITE_LOOP:		movx	@DPTR,A			;write SRAM
			inc	A
			mov	R0,DPH
			cjne	R0,#04h,WRITE_LOOP	;last SRAM address = 03FFh

			mov	TEST_COUNT,#00d

TEST_LOOP:		mov	DPTR,#0000h
			mov	TESTER,#00h

READ_LOOP:		movx	A,@DPTR			;read SRAM
			cjne	A,TESTER,ERROR		;tester holds what should be in SRAM
			inc	TESTER
			mov	R0,DPH
			cjne	R0,#04h,READ_LOOP	;last SRAM address = 03FFh

			inc	TEST_COUNT
			mov	A,TEST_COUNT
			cjne	A,#02d,TEST_LOOP	;test twice

			clr	SUCCESS			;no errors, success LED on
			sjmp	$

ERROR:			clr	FAIL			;fail LED on
			sjmp	$

;***************************************************************
			end